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1 ? fn8110.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary X3100, x3101 4 cell/3 cell 3 or 4 cell li-ion battery protection and monitor ic feature ? software selectable protection levels and variable protect dete ction/release times ? integrated fet drive circuitry ? cell voltage and current monitoring ? 0.5% accurate voltage regulator ? integrated 4kbit eeprom ? flexible power management with 1a sleep mode ? cell balancing control benefit ? optimize protection for chosen cells to allow maximum use of pack capacity. ? reduce component count and cost ? simplify implementation of gas gauge ? accurate voltage and current measurements ? record battery history to optimize gas gauge, track pack failures and monitor system use ? reduce power to extend battery life ? increase battery capacity and improve cycle life battery life description the X3100 is a protection and monitor ic for use in bat- tery packs consisting of 4 series lithium-ion battery cells. the x3101 is designed to work in 3 cell applica- tions. both devices provide internal over-charge, over- discharge, and over-current protection circuitry, internal eeprom memory, an internal voltage regulator, and internal drive circuitry for ex ternal fet devices that con- trol cell charge, discharge, and cell voltage balancing. over-charge, over-discharge, and over-current thresh- olds reside in an internal eeprom memory register and are selected independently via software using a 3mhz spi serial interface. detection and time-out delays can also be individually varied using external capacitors. using an internal analog multiplexer, the X3100 or x3101 allow battery parameters such as cell voltage and current (using a sense resistor) to be monitored externally by a separate mi crocontroller with a/d con- verter. software on this microcontroller implements gas gauge and cell balancing functionality in software. the X3100 and x3101 contai n a current sense ampli- fier. selectable gains of 10, 25, 80 and 160 allow an external 10 bit a/d converter to achieve better resolu- tion than a more expensive 14 bit converter. an internal 4kbit eepr om memory featuring idlock ? , allows the designer to partition and ?lock in? written battery cell/pack data. the X3100 and x3101 are each housed in a 28 pin tssop package. functional diagram protection circuit timing control & configuration ovt uvt oct fet control circuitry 4 kbit eeprom analog mux spi i/f 5vdc regulator internal voltage regulator power-on reset & status register vss vcell1 cb1 vcc rgp ovp/lmon uvp/ocp as0 as1 as2 ao s0 sck cs si cb3 cb2 cb4 vcell2 vcell3 vcell4/vss protection sample rate timer rgc rgo configuration register over-current protection & current sense vcs1 vcs2 over-charge over-discharge protection sense circuits control register data sheet april 11, 2005
2 fn8110.0 april 11, 2005 pin configuration X3100/x3101 ordering codes ordering number vcc limits package temperature range X3100v28 6v to 24v 28-lead tssop package -20c to +70c x3101v28 6v to 24v 28-lead tssop package -20c to +70c vcc rgp rgc rgo vcell1 cb1 vcell2 cb2 1 2 3 4 28 27 26 25 28 lead tssop uvp/ocp ovp/lmon cs sck vcell3 cb3 vcell4/vss* cb4 5 6 7 8 24 23 22 21 X3100/ so si as2 as1 vss vcs1 vcs2 ovt 9 10 11 12 20 19 18 17 as0 ao uvt oct 13 14 16 15 x3101 *for x3101, connect to ground. pin names pin symbol brief description 1 vcell1 battery cell 1 voltage input. this pin is used to monitor the voltage of this battery cell internally. the voltage of an individual cell can also be monitored externally at pin ao. the X3100 monitors 4 battery cells. the x3101 monitors 3 battery cells. 2cb1 cell balancing fet control output 1. this output is used to switch an external fet in order to perform cell voltage balancing control. this function can be used to adjust an individual cell voltage (e.g. during cell charging). cb1 can be driven high (vcc) or low (vss) to switch the external fet on/off. 3 vcell2 battery cell 2 voltage. this pin is used to monitor the voltage of this battery cell internally. the voltage of an individual cell can also be monitored externally at pin ao. the X3100 monitors 4 battery cells. the x3101 monitors 3 battery cells. 4cb2 cell balancing fet control output 2. these outputs are used to switch an external fets in order to perform cell voltage balancing control. this function can be used to adjust individual cell voltages (e.g. during cell charging). cb2 can be driven high (vcc) or low (vss) to switch the external fet on/off. 5 vcell3 battery cell 3 voltage. this pin is used to monitor the voltage of each battery cell internally. the voltage of an individual cell can also be monitored externally at pin ao. the X3100 monitors 4 battery cells. the x3101 monitors 3 battery cells. 6cb3 cell balancing fet control output 3. this output is used to switch an external fet in order to perform cell voltage balancing control. this function can be used to adjust an individual cell voltage (e.g. during cell charging). cb3 can be driven high (vcc) or low (vss) to switch the external fet on/off. 7 vcell4/ vss battery cell 4 voltag e (X3100) ground (x3101). this pin is used to monitor the voltage of this battery cell internally. the voltage of an individual cell can also be monitored externally at pin ao. the X3100 monitors 4 battery cells. the x3101 monitors 3 battery cells. for the x3101 device connect the vcell4/vss pin to ground. X3100, x3101
3 fn8110.0 april 11, 2005 8cb4 cell balancing fet control output 4. this output is used to switch an external fet in order to perform cell voltage balancing control. this function can be used to adjust individual cell voltages (e.g. during cell charging). cb4 can be driven high (vcc) or low (vss) to switch the external fet on/off. when using the x3101, the cb4 pin can be left unconnected, or the fet control can be used for other purposes. 9vss ground. 10 vcs1 current sense voltage pin 1. a sense resistor (r sense ) is connected between vcs1 and vcs2 (figure 1). r sense has a resistance in the order of 20m ? to 100m ? , and is used to monitor current flowing through the battery terminals, and protect against over-current conditions. the voltage at each end of r sense can also be monitored at pin ao. 11 vcs2 current sense voltage pin 2. a sense resistor (r sense ) is connected between vcs1 and vcs2 (figure 1). r sense has a resistance in the order of 20m ? to 100m ? , and is used to monitor current flowing through the battery terminals, and protect against over-current conditions. the voltage at each end of r sense can also be monitored at pin ao. 12 ovt over-charge detect/release time input. this pin is used to control the delay time (t ov ) associated with the detection of an over-charge condition (see section ?over-charge protection? on page 14). 13 uvt over-discharge detect /release time input. this pin is used to control the delay times associated with the detection (t uv ) and release (t uvr ) of an over-discharge (under-voltage) condition (see section ?over-discharge protection? on page 16). 14 oct over-current detect/release time input. this pin is used to control the delay times associated with the detection (t oc ) and release (t ocr ) of an over-current condition (see section ?over-current protection? on page 19). 15 ao analog multiplexer output. the analog output pin is used to exter nally monitor various battery param- eter voltages. the voltages which can be monitored at ao (see section ?analog multiplexer selection? on page 21) are: ? individual cell voltages ? voltage across the current sense resistor (r sense ) . this voltage is amplified with a gain set by the user in the control register (see section ?current monitor function? on page 21.) the analog select pins pins as0 - as2 select the desired voltage to be monitored on the ao pin. 16 as0 analog output select pin 0. these pins select which voltage is to be multiplexed to the output ao (see section ?sleep control (slp)? on page 11 and section ?current monitor function? on page 21) 17 as1 analog output select pin 1. these pins select which voltage is to be multiplexed to the output ao (see section ?sleep control (slp)? on page 11 and section ?current monitor function? on page 21) 18 as2 analog output select pin 2. these pins select which voltage is to be multiplexed to the output ao (see section ?sleep control (slp)? on page 11 and section ?current monitor function? on page 21) 19 si serial data input. si is the serial data input pin. all opcodes, byte addresses, and data to be written to the device are input on this pin. 20 so serial data output. so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. while cs is high, so will be in a high impedance state. note: si and so may be tied together to form one line (si/ so). in this case, all serial data communication with the X3100 or x3101 is undertaken over one i/o line. this is permitted only if no simultaneous read/write operations occur. 21 sck serial data clock input. the serial clock controls the serial bus timing for data input and output. op- codes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. 22 cs chip select input pin. when cs is high, the device is deselected and the so output pin is at high im- pedance. cs low enables the spi serial bus. pin names (continued) pin symbol brief description X3100, x3101
4 fn8110.0 april 11, 2005 23 ovp/ lmon over-charge voltage protection output/load monitor output. this one pin performs two functions depending upon the present mode of operation of the X3100 or x3101. over-charge voltage protection (ovp) this pin controls the switching of the battery pack ch arge fet. this power fet is a p-channel device. as such, cell charge is possible when ovp/lmon=v ss , and cell charge is prohibited when ovp/lmo = v cc . in this configuration the X3100 and x3101 turn off the charge voltage when the cells reach the over-charge limit. this prevents damage to the battery cells due to the application of charging voltage for an extended period of time (see section ?over-charge protection? on page 14). load monitor (lmon) in over-current protection mode, a small test current (7.5a typ.) is passed out of this pin to sense the load resistance. the measured load resistance deter mines whether or not the X3100 or x3101 returns from an over-current protection mode (see se ction ?over-current protection? on page 19). 24 uvp/ ocp over-discharge protection output/over-current protection output. pin uvp/ocp controls the bat- tery cell discharge via an external power fet. this p-channel fet allows cell discharge when uvp/ocp=vss, and prevents cell discharge when uvp/ocp=vcc. the X3100 and x3101 turn the ex- ternal power fet off when the X3100 or x3101 detects either: over-discharge protection (uvp) in this case, pin 24 is referred to as ?over-di scharge (under-voltage) protec tion (uvp)? (see section ?over-discharge protection? on page 16). uvp/ocp turn s off the fet to prevent damage to the battery cells by being discharged to excessively low voltages. over-current protection (ocp) in this case, pin 24 is referred to as ?over-current protection (ocp)? (see section ?over-current protec- tion? on page 19). uvp/ocp turns off the fet to prevent damage to the battery pack caused by exces- sive current drain (e.g. as in the case of a surge current resulting from a stalled disk drive). 25 rgo voltage regulator output pin. this pin is an input that connects to the collector of an external pnp tran- sistor. the voltage at this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage for the device. 26 rgc voltage regulator control pin. this pin connects to the base of an external pnp transistor and controls the transistor turn on. 27 rgp voltage regulator protection pin. this pin is an input that connects to the emitter of an external pnp transistor and an external current limit resistor and provides a current limit voltage. 28 vcc power supply. this pin is provides the voltage for fet control, regulator operation, and wake-up circuits. pin names (continued) pin symbol brief description X3100, x3101
5 fn8110.0 april 11, 2005 principles of operation the X3100 and x3101 provide two distinct levels of functionality and battery cell protection: first, in normal mode, the device periodically checks each cell for an over-charge and over-discharge state, while continuously watching for a pack over-current condition. a protection mode violation results from an over-charge, over-discharge, or over-current state. the thresholds for these states are selected by the user through software. when one of these conditions occur, a discharge fet or a charge fet or both fets are turned off to protect the battery pack. in an over- discharge condition, the X3100 and x3101 devices go into a low power sleep mode to conserve battery power. during sleep, the voltage regulator turns off, removing power from the microcontroller to further reduce pack current. second, in monitor mode, a microcontroller with a/d converter measures battery cell voltage and pack cur- rent via pin ao and the X3100 or x3101 on-board mux. the user can thus implement protection, charge/dis- charge, cell balancing or gas gauge software algorithms to suit the specif ic application and char acteristics of the cells used. while monitoring these voltages, all protec- tion circuits are on continuously. in a typical application, the microcontroller is also pro- grammed to provide an smbus interface along with the smart battery system in terface protocols. these additions allow an X3100 or x3101 based module to adhere to the latest indus try battery pack standards. typical application circuit the X3100 and x3101 have been designed to operate correctly when used as connected in the typical appli- cation circuit (see figure 1 on page 5). the power mosfet?s q1 and q2 are referred to as the ?discharge fet? and ?charge fet,? respectively. since these fets are p-channel devices, they will be on when the gates are at v ss , and off when the gates are at v cc . as their names imply, the discharge fet is used to control cell discharge, while the charge fet is used to control cell charge. diode d1 allows the battery cells to receive charge even if the discharge fet is off, while diode d2 allows the cells to dis- charge even if the charge fet is off. d1 and d2 are integral to the power fets. it should be noted that the cells can neither charge nor discharge if both the charge fet and discharge fet are off. power to the X3100 or x3101 is applied to pin vcc via diodes d6 and d7. these diodes allow the device to be powered by the li-ion battery cells in normal oper- ating conditions, and allow the device to be powered by an external source (such as a charger) via pin p+ when the battery cells are being charged. these diodes should have sufficient current and voltage rat- ings to handle both cases of battery cell charge and discharge. the operation of the voltage regulator is described in section ?voltage regulator? on page 22. this regulator provides a 5vdc0.5% output. the capacitor (c1) connected from rgo to ground provides some noise filtering on the rgo output. the recommended value is 0.1f or less. the value chosen must allow v rgo to decay to 0.1v in 170ms or less when the X3100 or x3101 enter the sleep mode. if the decay is slower than this, a resistor (r1) can be placed in parallel with the capacitor. during an initial turn-on period (t pur + t oc ), v rgo has a stable, regulated output in the range of 5vdc 10% (see figure 2). the selection of the microcontrol- ler should take this into consideration. at the end of this turn on period, the X3100 and x3101 ?self-tunes? the output of the voltage regulator to 5v+/-0.5%. as such, v rgo can be used as a reference voltage for the a/d converter in the microc ontroller. repeated power- up operations, consistently re-apply the same ?tuned? value for v rgo . figure 1 shows a battery pack temperature sensor implemented as a simple resistive voltage divider, uti- lizing a thermistor (r t ) and resistor (r t ?). the voltage v t can be fed to the a/d input of a microcontroller and used to measure and monitor the temperature of the battery cells. r t ? should be chosen with consideration of the dynamic resistance range of r t as well as the input voltage range of the microcontroller a/d input. an output of the microcontroller can be used to turn on the thermistor divider to a llow periodic turn-on of the sensor. this reduces power consumption since the resistor string is not always drawing current. diode d3 is included to fac ilitate load moni toring in an over-current protection mode (see section ?over-cur- rent protection? on page 19), while preventing the flow of current into pin ovp/lmon during normal opera- tion. the n-channel transistor turns off this function during the sleep mode. resistor r pu is connected across the gate and drain of the charge fet (q2). the discharge fet q1 is turned off by the X3100 or x3101, and hence the volt- age at pin ovp/lmon will be (at maximum) equal to the voltage of the battery terminal, minus one forward biased diode voltage drop (v p+ - v d7 ). since the drain of q2 is connected to a higher potential (v p+ ) a pull-up resistor (r pu ) in the order of 1m ? should be used to ensure that the charge fet is completely turned off when ovp/lmon = v cc . X3100, x3101
6 fn8110.0 april 11, 2005 the capacitors on the v cell1 to v cell4 inputs are used in a first order low pass filter configuration, at the battery cell voltage monitoring inputs (vcell1 - vcell4) of the X3100 or x310 1. this filter is used to block any unwanted interference signals from being inadvertently injected into the monitor inputs. these interference signals may result from: ? transients created at battery contacts when the bat- tery pack is being connec ted/disconnected from the charger or the host. ? electrostatic discharge (esd) from some- thing/someone touching the battery contacts. ? unfiltered noise that exists in the host device. ? rf signals which are induced into the battery pack from the surrounding environment. such interference can cause the X3100 or x3101 to operate in an unpredictable manner, or in extreme cases, damage the device. as a guide, the capacitor should be in the order of 0.01f and the resistor, should be in the order of 10k ? . the capacitors should be of the ceramic type. in order to minimize interfer- ence, pcb tracks should be made as short and as wide as possible to reduce their impedance. the bat- tery cells should also be placed as close to the X3100 or x3101 monitor inputs as possible. resistors r cb and the associated n-channel mosfet?s (q 6 - q 9 ) are used for battery cell voltage balancing. the X3100 and x3101 provide internal drive circuitry which allows the user to switch fets q 6 - q 9 on or off via the microcontroller and spi port (see section ?cell voltage balance control (cbc1-cbc4)? on page 12). when any of the these fets are switched on, a current, limited by resistor r cb , flows across the par- ticular battery cell. in doing so, the user can control the voltage across each individu al battery cell. this is important when using li-ion battery cells since imbal- ances in cell voltages can, in time, greatly reduce the usable capacity of the batte ry pack. cell voltage bal- ancing may be implemented in various ways, but is usually performed towards the end of cell charging (?top-of-charge method?). values for r cb will vary according to the specific application. the internal 4kbit eeprom memory can be used to store the cell characteristics for implementing such functions as gas gauging, battery pack history, charge/discharge cycles, and minimum/maximum con- ditions. battery pack manufacturing data as well as serial number information can also be stored in the eeprom array. an spi serial bus provides the com- munication link to the eeprom. a current sens e resistor (r sense ) is used to measure and monitor the current flowing into/out of the battery terminals, and is used to protect the pack from over- current conditions (see sect ion ?over-current protec- tion? on page 19). r sense is also used to externally monitor current via a microcontroller (see section ?cur- rent monitor function? on page 21). fets q4 and q5 may be required on general pur- pose i/os of the microcontroller that connect outside of the package. in some cases, without fets, pull-up resistors external to the pack force a voltage on the v cc pin of the microcontroller during a pack sleep con- dition. this voltage can affect the proper tuned voltage of the X3100/x3101 regulator. these fets should be turned-on by the microcontroller. (see figure 1.) power-on sequence initial connection of the li-ion cells in the battery pack will not normally power-up th e battery pack. instead, the X3100 or x3101 enters and remains in the sleep mode. to exit th e sleep mode, after the initial power- up sequence, or following any other sleep mode, a minimum of 16v (X3100 v slr ) or 12v (x3101 v slr ) is applied to the vcc pin, as would be the case during a battery charge condition. (see figure 2.) when v slr is applied to vcc, the analog select pins (as2 - as0) and the spi communication pins (cs , clk, si, so) must be low, so the X3100 and x3101 power-up correctly into the normal operating mode. this can be done by using a power-on reset circuit. when entering the normal operating mode, either from initial power-up or follo wing the sleep mode, all bits in the control register are zero. with uvpc and ovpc bits at zero, the charge and discharge fets are off. the microcontroller must turn these on to activate the pack. the microcontroller would typically check the voltage and current levels prior to turning on the fets via the spi port. the software should prevent turning on the fets throughout an initial measurement/cali- bration period. the duration of this period is t ov + 200ms or t uv + 200ms, whichever is longer. X3100, x3101
7 fn8110.0 april 11, 2005 figure 1. typical application circuit r cb . v ss vcs1 vcs2 ovt uvt oct vcell1 cb1 cb3 vcell4/v ss vcell3 X3100/x3101 cb2 v cc rgp rgc rgo ovp/ uvp/ c, asic 100 r cb 100 100 100 r cb r cb q6 q7 q8 q9 0.01uf 0.01uf 0.01uf 0.01uf c ov c oc c uv r lmt i lmt q 3 q 1 q 2 r pu d 3 i lmon p+ p- d 6 d 7 r t ? r t v t vcell2 r sense 3 or 4 li-ion cells ? discharge fet charge fet v rgo cb4 d 1 d 2 b+ b- ocp 0.1f 1f q 10 transistor recommendations q1, q2 = si4435 q3 = 2n3906 q4 - q10 = 2n7002 r por c por as0 as1 as2 ao cs sck so si lmon smbclk smbdata 28 27 26 25 24 23 21 20 19 22 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1m 100 100 fets q4 and q5 are needed only if external pull-ups on the smbus lines cause volt- age to appear at the uc vcc pin during sleep mode. 1m q 4 q5 bat54 bat54 a/d a/d input a/d input v cc reset gp i/o gp i/o i/o gp set high after power- uppower- down to enable choose r1 and c1 such that v rgo goes to 0.1v (or less) in 170ms (or less) when entering the sleep mode (at 25 o c). for the x3101, or X3100 when 3 cells are used, vcell4/v ss must be tied to ground (vss). cb4 is left unconnected. c1 r1 ref (optional) X3100, x3101
8 fn8110.0 april 11, 2005 figure 2. power-up timing (initial power-up or after sleep mode) vcc v rgo t oc 2ms (typ.) t pur 5v10% (stable and repeatable) 0v 0v v rgo tuned to 5v0.5% vrgs voltage regulator output status ocds over-current detection status vrgs+ocds 1 = X3100/1 in over-current protection mode 0 = X3100/1 not in over-current protection mode 0 = X3100/1 not in over-current protection mode and vrgo tuned 1 = X3100/1 in over-current protection mode or vrgo not yet tuned status register bit 0 1 0 5v v slr 1 0 1 as2_as0 0 (internal signal) (internal signal) cces+ovds status register bit 2 (swcen = 0) ovds status register bit 2 (swcen = 1) 0 0 t ov +200ms 1 1 from spi port t ov + 200ms or t uv + 200ms (whichever is longer) 0 = v cell > v ce or X3100/1 not in over-charge protection mode 1 = v cell < v ce or X3100/1 in over-charge protection mode 0 = X3100/1 not in over-charge protection mode 1 = X3100/1 in over-charge protection mode microcontroller charge, discharge fets can be turned on here. any read or write operation, except turn-on of fets can start here. X3100, x3101
9 fn8110.0 april 11, 2005 configuration register the X3100 and x3101 can be configured for specific user requirements using the configuration register. table 1. configuration register functionality table 2. configuration register?upper byte table 3. configuration register?lower byte over-charge voltage settings vov1 and vov0 control the cell over-charge level. see section ?over-charge protection? on page 14. table 4. over-charge voltage threshold selection over-discharge settings vuv1 and vuv0 control the cell over-discharge (under voltage threshold) level. see section ?over-dis- charge protection? on page 16. over-current settings voc1 and voc0 control the pack over-current level. see section ?over-current protection? on page 19. table 6. over-current threshold voltage selection. cell charge enable settings vce1, vce0 and swcen control the pack charge enable function. swcen enables or disables a circuit that prevents charging if the cells are at too low a volt- age. vce1 and vce0 select the voltage that is recog- nized as too low. see section ?sleep mode? on page 16. table 7. cell charge enable function bit(s) name function 0-5 ? (don?t care) 6 swcen switch cell charge enable threshold function on/off 7 celln set the number of li-ion battery cells used (3 or 4) 8-9 vce1-vce0 select cell charge enable threshold 10-11 voc1-voc0 select over-current threshold 12-13 vuv1-vuv0 select over-discharge (under voltage) threshold 14-15 vov1-vov0 select over-charge voltage threshold 15 14 13 12 11 10 9 8 vov1 vov0 vuv1 vuv0 voc1 voc0 vce1 vce0 X3100 default = 33h; x3101 default = 03h. 7 6 543210 cellnswcenxxxxxx X3100 default = c0h; x3101 default = 40h. configuration register bits operation vov1 vov0 00v ov = 4.20v (default) 01v ov = 4.25v 10v ov = 4.30v 11v ov = 4.35v table 5. over-discharge threshold selection. configuration register bits operation vuv1 vuv0 X3100 x3101 00v uv = 1.95v v uv = 2.25v (x3101 default) 01v uv = 2.05v v uv = 2.35v 10v uv = 2.15v v uv = 2.45v 11v uv = 2.25v (X3100 default) v uv = 2.55v configuration register bits operation voc1 voc0 00v oc = 0.075v (default) 01v oc = 0.100v 10v oc = 0.125v 11v oc = 0.150v configuration register bit operation swcen 0 charge enable function: on 1 charge enable function: off X3100, x3101
10 fn8110.0 april 11, 2005 table 8. cell charging threshold voltage selection. cell number selection the X3100 is designed to operate with four (4) li-ion battery cells. the x3101 is designed to operate with three (3) li-ion battery cells. the celln bit of the con- figuration register (table 9) sets the number of cells recognized. for the x3101, the value for celln should always be zero. table 9. selection of number of battery cells 1 the configuration register consists of 16 bits of novram memory (table 2, table 3). this memory features a high-speed static ram (sram) overlaid bit- for-bit with non-volatile ?shadow? eeprom. an auto- matic array recall operation reloads the contents of the shadow eeprom into the sram configuration regis- ter upon power-up (figure 3). figure 3. power-up of configuration register the configuration register is designed for unlimited write operations to sram, and a minimum of 1,000,000 st ore operations to the eeprom. data retention is specified to be greater than 100 years. it should be noted that the bits of the shadow eeprom are for the dedicat ed use of th e configura- tion register, and are not part of the general purpose 4kbit eeprom array. t he wcfig command writes to the configuration reg- ister, see table 30 and section ?X3100/x3101 spi serial communication? on page 23. after writing to this regist er using a wcfig instruction, data will be stored only in the sram of the configura- tion register. in order to store data in shadow eeprom, a wren instruct ion, followed by a eewrite to any address of the 4kbit eeprom mem- ory array must occur, see figure 4. this sequence ini- tiates an internal nonvolat ile write cycle which permits data to be stored in the shadow eeprom cells. it must be noted that even though a eewrite is made to the general purpose 4kbi t eeprom array, the value and address to which it is wr itten, is unimportant. if this procedure is not followed, the configuration register will power-up to the last previously stored values fol- lowing a power-down sequence. configuration register bits operation vce1 vce0 00v ce = 0.5v 01v ce = 0.80v 10v ce = 1.10v 11v ce = 1.40v (default) configuration register bit operation celln 1 4 li-ion battery cells (X3100 default) 0 3 li-ion battery cells (X3100 or x3101) 1. in the case that the X3100 or x3101 is configured for use with only three li-ion battery cells (i.e. celln = 0), then vcell4 (pin 7) must be tied to vss (pin 9) to ensure correct operation. configuration register (sram) shadow eeprom recall recall upper byte lower byte X3100, x3101
11 fn8110.0 april 11, 2005 figure 4. writing to configuration register control register the control register is rea lized as two bytes of vola- tile ram (table 10, table 11). this register is written using the wcntr instruction, see table 30 and section ?X3100/x3101 spi serial communication? on page 23. table 10. control register?upper byte table 11. control register?lower byte since the control register is volatile, data will be lost following a power-down and power-up sequence. the default value of the control register on initial power-up or when exitin g the sleep mode is 00h (for both upper and lower bytes respectively). the functions that can be manipulated by the control register are shown in table 12. table 12. control register functionality sleep control (slp) setting the slp bit to ?1? forces the X3100 or x3101 into the sleep mode, if v cc < v slp . see section ?sleep mode? on page 16. table 13. sleep mode selection 15 14 13 12 11 10 9 8 cbc4 cbc3 cbc2 cbc1 uvpc ovpc csg1 csg0 7 6543210 slp00xxxxx configuration register (sram = old value) write enable write to 4kbit eeprom power-down power-up store (new value) in shadow eeprom configuration register (sram = old value) wcfig (new value) data recalled no yes wren eewrite configuration register (sram = new value) power-up configuration register (sram = new value) from shadow eeprom to sram data recalled from shadow eeprom to sram data recalled from shadow eeprom to sram power-down- power-on bit(s) name function 0-4 ? (don?t care) 5,6 0, 0 reserved?write 0 to these locations. 7 slp select sleep mode. 8,9 csg1, csg0 select current sense voltage gain 10 ovpc ovp control: switch pin ovp = v cc /v ss 11 uvpc uvp control: switch pin uvp = v cc /v ss 12 cbc1 cb1 control: switch pin cb1 = v cc /v ss 13 cbc2 cb2 control: switch pin cb2 = v cc /v ss 14 cbc3 cb3 control: switch pin cb3 = v cc /v ss 15 cbc4 cb4 control: switch pin cb4 = v cc /v ss control register bits operation slp 0 normal operation mode 1 device enters sleep mode X3100, x3101
12 fn8110.0 april 11, 2005 current sense gain (csg1, csg0) these bits set the gain of the current sense amplifier. these are x10, x25, x80 and x160. for more detail, see section ?current monitor function? on page 21. table 14. current sense gain control charge/discharge control (ovpc, uvpc) the ovpc and uvpc bits allow control of cell charge and discharge externally, via the spi port. these bits control the ovp/lmon and uvp/ocp pins, which in turn control the external power fets. using p-channel power fets ensures that the fet is on when the pin voltage is low (vss), and off when the pin voltage is high (vcc). ovp/lmon and uvp/ocp can be controlled by using the wcntr instruction to se t bits ovpc and uvpc in the control register (see page 11). table 15. uvp/ovp control it is possible to set/change the values of ovpc and uvpc during a protection mode. a change in the state of the pins ovp/lmon and uvp/ocp, however, will not take place until the device has returned from the protection mode. cell voltage balance control (cbc1-cbc4) this function can be used to adjust individual battery cell voltage during charging. pins cb1 - cb4 are used to control external power s witching devices. cell volt- age balancing is achieved via the spi port. table 16. cb1?cb4 control cb1 - cb4 can be controlled by using the wcntr in- struction to set bits cbc1 - cbc4 in the control register (table 16). status register the status of the X3100 or x3101 can be verified by using the rdstat command to read the contents of the status register (table 17). table 17. status register. the function of each bit in the status register is shown in table 18. bit 0 of the status regi ster (vrgs+ocds) actually indicates the status of two conditions of the X3100 or x3101. voltage regulator st atus (vrgs) is an inter- nally generated signal which indicates that the output of the voltage regulator (vrgo) has reached an out- put of 5vdc 0.5%. in this case, the voltage regulator is said to be ?tuned?. before the signal vrgs goes low (i.e. before the voltage regulator is tuned), the voltage at the output of the regulator is nominally 5vdc 10% (see section ?voltage regulator? on page 22.) over- current detection status (o cds) is anoth er internally generated signal which indicates whether or not the X3100 or x3101 is in over-current protection mode. signals vrgs and ocds are logically or?ed together (vrgs + ocds) and written to bit 0 of the status reg- ister (see table 18, table 17 and figure 2). control register bits operation csg1 csg0 0 0 set current sense gain = x10 0 1 set current sense gain = x25 1 0 set current sense gain = x80 1 1 set current sense gain = x160 control register bits operation ovpc uvpc 1 x pin ovp = v ss (fet on) 0 x pin ovp = v cc (fet off) x 1 pin uvp = v ss (fet on) x 0 pin uvp = v cc (fet off) control register bits operation cbc4 cbc3 cbc2 cbc1 xxx1set cb1 = v cc (on) xxx0set cb1=v ss (off) xx1xset cb2 = v cc (on) xx0xset cb2 = v ss (off) x1xxset cb3 = v cc (on) x0xxset cb3 = v ss (off) 1xxxset cb4 = v cc (on) 0xxxset cb4 = v ss (off) 76543 2 1 0 00000 cces+ ovds uvds vrgs+ ocds X3100, x3101
13 fn8110.0 april 11, 2005 bit 1 of the status register simply indicates whether or not the X3100 or x3101 is in over-discharge protec- tion mode. bit 2 of the status register (cces+ovds) indicates the status of two conditions of the X3100 or x3101. cell charge enable status (cces) is an internally generated signal which indica tes the status of any cell voltage (v cell ) with respect to the cell charge enable voltage (v ce ). over-charge volt age detection status (ovds) is an internally generated signal which indi- cates whether or not the X3100 or x3101 is in over- charge protection mode. when the cell charge enable function is switched on (configuration bit swcen=0), the signals cces and ovds are logically or?ed (cces+ovds) and written to bit 2 of the status register. if the cell charge enable function is switched off (configuration bit swcen=1), then bit 2 of the st atus register effectively only represents information about the over-charge sta- tus (ovds) of the X3100 or x3101 (see table 18, table 17 and figure 2). table 18. status register functionality. notes: ? this bit is set in the configuration register. X3100/x3101 internal prot ection functions the X3100 and the x3101 provide periodic monitoring (see section ?periodic protection monitoring? on page 13) for over-charge and over-discharge states and continuous monitoring for an over-current state. it has automatic shutdown when a protection mode is encountered, as well as automatic return after the device is released from a protection mode. when sam- pling voltages through the analog port (monitor mode), over-charge and over-discharge protection monitoring is also performed on a continuous basis. voltage thresholds for each of these protection modes (v ov , v uv , and v oc respectively) can be individually selected via software and stored in an internal non-vol- atile register. this feature allows the user to avoid the restrictions of mask programmed voltage thresholds, and is especially useful during prototype/evaluation design stages or when cells with sli ghtly different characteris- tics are used in an existing design. delay times for the detection of, and release from protec- tion modes (t ov , t uv /t uvr , and t oc /t ocr respectively) can be individually varied by setting the values of external capacitors connect ed to pins ovt, uvt, oct. periodic protection monitoring in normal operation, the analog select pins are set such that as2 = l, as1 = l, as0 = l. in this mode the X3100 and x3101 conserve power by sampling the cells for over or over-discharge conditions. in this state over-charge and over-discharge protec- tion circuitry are usually off, but are periodically switched on by the internal protection sample rate timer (psrt). the over-charge and over-discharge protection circuitry is on for approximately 2ms in each 125ms period. over-current monitoring is continuous. in monitor mode (see page 21) over-charge and over- discharge monitoring is also continuous. bit(s) name description case status interpretation 0 vrgs+ocds voltage regulator status + over-current detection status -1v rgo not yet tuned (v rgo = 5v 10%) or X3100/x3101 in over-current protection mode. 0v rgo tuned (v rgo = 5v 0.5%) and X3100/x3101 not in over-current protection mode. 1 uvds over-discharge detection status - 1 X3100/x3101 in over-discharge protection mode 0 X3100/x3101 not in over-discharge protection mode 2 cces+ovds cell charge enable status + over-charge detection status swcen =0 ? 1v cell < v ce or X3100/x3101 in over-charge protection mode 0v cell > v ce and X3100/x3101 not in over-charge protection mode swcen =1 ? 1 X3100/x3101 in over-charge protection mode 0 X3100/x3101 not in over-charge protection mode 3 - 7 - - 0 not used (always return zero) X3100, x3101
14 fn8110.0 april 11, 2005 over-charge protection the X3100 and x3101 monitor the voltage on each battery cell (v cell ). if for any cell, v cell > v ov for a time exceeding t ov , then the charge fet will be switched off (ovp/lmon = v cc ). the device has now entered over-charge protection mode (figure 5). the status of the discharge fet (via pin uvp) will remain unaffected. while in over-charge protection mode, it is possible to change the state of the ovpc bit in the control register such that ovp/lmon = vss (charge fet = on). although the ovpc bit in the control register can be changed, the chang e will not be seen at pin ovp until the X3100 or x3101 returns from over-charge protec- tion mode. the over-charge detection delay t ov , is varied using a capacitor (c ov ) connected between pin ovt and gnd. a typical delay time is shown in table 10. the delay t ov that results from a particular capacitance c ov , can be approximated by the following linear equation: t ov (s) 10 x c ov (f). table 19. typical over-charge detection time the device further continues to monitor the battery cell voltages, and is released from over-charge protection mode when v cell < v ovr , for all cells. when the X3100 or x3101 is released from over-charge protec- tion mode, the charge fet is automatically switched on (ovp/lmon = v ss ). when the device returns from over-charge protection mode , the status of the dis- charge fet (pin uvp/ocp) remains unaffected. the value of v ov can be selected from the values shown in table 4 by setting bits vov1, vov0. these bits are set by using the wc fig instruction to write to the configuration register. figure 5. over-charge protection mode?event diagram symbol c ov delay t ov 0.1f 1.0s (typ) v cell ovp/lmon normal operation mode over-charge v ov v ovr t ov protection mode normal operation mode v cc v ss event 0 1 2 3 X3100, x3101
15 fn8110.0 april 11, 2005 table 20. over-charge protection mode?event diagram description event event description [0,1) ? discharge fet is on (uvp/ocp = v ss ). ? charge fet is on (ovp/lmon = v ss ), and hence battery cells are permitted to receive charge. ? all cell voltages (v cell - v cell4 ) are below the over-charge voltage threshold (v ov ). ? the device is in normal operation mode (i.e. not in a protection mode). [1] ? the voltage of one or more of the battery cells (v cell ), exceeds v ov . ? the internal over-charge detection delay timer begins counting down. ? the device is still in normal operation mode (1,2) the internal over-charge detection delay timer continues counting for t ov seconds. [2] the internal over-charge detection delay timer times out and v cell still exceeds v ov. ? therefore, the internal over-charge sense circui try switches the charge fet off (ovp/lmon=vcc). ? the device has now entered over-charge protection mode. (2,3) while in over-charge protection mode: ? the battery cells are permitted to discharge via the discharge fet, and diode d 2 across the charge fet ? the X3100 or x3101 monitors the voltages v cell1 - v cell4 to determine whether or not they have all fallen below the ?return from over-charge threshold? (v ovr ). ? (it is possible to change the status of uvp/ocp or ovp/lmon using the control register) [3] ? all cell voltages fall below v ovr ?the device is now in normal operation mode. ? the X3100/x3101 automatically switches charge fet = on (ovp/lmon = vss) ? the status of the discharge fet remains unaffected. ? charging of the battery cells can now resume. X3100, x3101
16 fn8110.0 april 11, 2005 over-discharge protection if v cell < v uv , for a time exceeding t uv , the cells are said to be in a over-discharge state (figure 6). in this instance, the X3100 and x3101 automatically switch the discharge fet off (uvp/ocp = vcc), and then enter sleep mode. the over-discharge (under-voltage) value, v uv , can be selected from the values s hown in table 5 by setting bits vuv1, vuv0 in the configuration register. these bits are set using the wcfig command. once in the sleep mode, the following steps must occur before the X3100 or x3101 allows the battery cells to discharge: ? the X3100 and x3101 must wake from sleep mode (see section ?voltage regulator? on page 22). ? the charge fet must be switched on by the micro- controller (ovp/lmon=v ss ), via the control register (see section ?control register functionality? on page 11). ? all battery cells must sa tisfy the condition: v cell > v uvr for a time exceeding t uvr . ? the discharge fet must be switched on by the microcontroller (uvp/ocp=v ss ), via the control reg- ister (see section ?control register functionality? on page 11) the times t uv /t uvr are varied using a capacitor (c uv ) connected between pin uvt and gnd (table 13). the delay t uv that results from a particular capacitance c uv , can be approximated by the following linear equation: t uv (s) 10 x c uv (f) t uvr (ms) 70 x c uv (f) sleep mode the X3100 or x3101 can enter sleep mode in two ways: i) the device enters the over-discharge protection mode. ii) the user sends the device into sleep mode using the control register. a sleep mode can be induced by the user, by setting the slp bit in the control register (table 13) using the wcntr instruction. in sleep mode, power to all internal circuitry is switched off, minimizing the current drawn by the device to 1a (max). in this state, the discharge fet and the charge fet are switched off (ovp/lmon=v cc and uvp/ocp=v cc ), and the 5vdc regulated output (v rgo ) is 0v. control of uvp/ocp and ovp/lmon via bits uvpc and ovpc in the con- trol register is also prohibited. the device returns from sleep mode when v cc v slr . (e.g. when the battery terminals are connected to a battery charger). in this case, the X3100 or the x3101 restores the 5vdc regulat ed output (section ?voltage regulator? on page 22), and communication via the spi port resumes. if the cell charge enable function is enabled when v cc rises above v slr , the X3100 and x3101 internally verifies that the individual battery cell voltages (v cell ) are larger than the cell charge enable voltage (v ce ) before allowing the fets to be turned on. the value of v ce is selected by using the wcfig command to set bits vce1?vce0 in the configuration register. only if the condition ? v cell > v ce ? is satisfied can the state of charge and discharge fets be changed via the control register . otherwise, if v cell < v ce for any battery cell then both the charge fet and the dis- charge fet are off (ovp/lmon=vcc and uvp/ocp=v cc ). thus both charge and discharge of the battery cells via terminals p+ / p- is prohibited 1 . the cell charging threshold function can be switched on or off by the user, by setting bit swcen in the configuration register (table 7) using the wcfig com- mand. in the case that this cell charge enable function is switched off, then v ce is effectively set to 0v. neither the X3100 nor the x3101 enter sleep mode (automatically or manually, by setting the slp bit) if v cc v slr . this is to ensure that the device does not go into a sleep mode while the battery cells are at a high voltage (e.g. during cell charging). table 21. typical over-discharge delay times symbol description c uv delay t uv over-discharge detection delay 0.1f 1.0s (typ) t uvr over-discharge release time 0.1f 7ms (typ) 1. in this case, charging of the battery may resume only if the cell charge enable function is switched off by setting bit swcen = 1 in the configuration register (see above, ?configuration register functionality? on page 9). X3100, x3101
17 fn8110.0 april 11, 2005 figure 6. over-discharge protection mode?event diagram t uvr v ce vcell uvp/ocp rgo over-discharge protection mode sleep mode 0v 5v t uv v uvr v uv event 0 1 2 3 4 vcc 5 v slr v cc v ss cell charge prohibited if swcen=0 and v cell < v ce note 1: if swen = 0 and v cell < v ce , then ovp/lmon stays high and charging is prohibited. ovp/lmon note 1, 2 v ss v cc note 2: ovp/lmon stays high until the microcontroller writes a ?1? to the ovpc bit in the control register. this sets the signal low, which turns on the charge fet. it cannot be turned on prior to this time. note 3: uvp/ocp stays high until the microcontroller writes a ?1? to the u vpc bit in the control register. this sets the signal low, wh ich turns on the discharge fet. the fet cannot be turned on prior to this time. note 3 the longer of tov+200ms or tuv+200ms 0.7v table 22. over-discharge protection mode?event diagram description event event description [0,1) ? charge fet is on (ovp/lmon = v ss ) ? discharge fet is on (uvp/ocp = v ss ), and hence battery cells are permitted to discharge. ? all cell voltages (vcell 1 - vcell 4 ) are above the over-discharge threshold voltage (v uv ). ? the device is in normal operation mode (i.e. not in a protection mode). [1] ? the voltage of one or more of the battery cells (v cell ), falls below v uv . ? the internal over-discharge detection delay timer begins counting down. ? the device is still in normal operation mode (1,2) the internal over-discharge detection delay timer continues counting for t uv seconds. [2] ? the internal over-discharge detection delay timer times out, and v cell is still below v uv. ? the internal over-discharge sense circuitry swit ches the discharge fet off (uvp/ocp = vcc). ? the charge fet is switched off (ovp/lmon = v cc ). ? the device has now entered over-discharge protection mode. ? at the same time, the device enters sleep m ode (see section ?voltage regulator? on page 22). (2,3) while device is in sleep (in over-discharge protection) mode: ? the power to all internal circuits is switc hed off limiting power consumption to less than 1a. ? the output of the 5vdc voltage regulator (rgo) is 0v. ? access to the X3100/x3101 via the spi port is not possible. X3100, x3101
18 fn8110.0 april 11, 2005 [3] return from sleep mode (but still in over-discharge protection mode): ? vcc rises above the ?return from sleep mode threshold voltage? (v slr )?this would normally occur in the case that the battery pack was connected to a charger. the X3100/x3101 is now powered via p+/p-, and not the battery pack cells. ? power is returned to all internal circuitry ? 5vdc output is returned to the regulator output (rgo). ? access is enabled to the X3100/x3101 via the spi port. ? the status of the discharge fet remains off (it is po ssible to change the status of uvpc in the control register, although it will have no effect at this time). (3,4) if the cell charge enable function is switched on and v cell > v ce or charge enable function is switched off ? the X3100/x3101 initiates a reset operation that takes the longer of t ov + 200ms or t uv + 200ms to complete. do not write to the fet control bits during this time. ? the charge fet is switched on (ovp/l mon = vss) by the microcontroller by writing a ?1? to the ovpc bit in the control register. ? the battery cells now receive charge via the charge fet and diode d1 across the discharge fet (which is off). ? the X3100/x3101 monitors the v cell voltage to determine whether or not it has risen above v uvr . if the cell charge enable function is switched on and v cell < v ce ? charge/discharge of the battery cells via p+ is no longer permitted (charge fet and discharge fet are held off). ? (charging may re-commence only when the cell charge enable function is switched off - see sections: ?configuration register? page 4, and ?sleep mode? page 17.) [4] ? the voltage of all of the battery cells (v cell ), have risen above v uvr . ? the internal over-discharge release timer begins counting down. ? the X3100/x3101 is still in over-discharge protection mode. (4,5) ? the internal over-discharge release timer continues counting for t uvr seconds. ? the X3100/x3101 should be in monitor mode (as2:as0 not all low) for recovery time based on t uvr . other- wise recovery is based on two successive samples about 120ms apart. [5] ? the internal over-discharge release timer times out, and v cell is still above v uvr. ? the device returns from over-discharge protection mode, and is now in normal operation mode. ? the charger voltage can now drop below vslr and the X3100/x3101 will not go back to sleep. ? the discharge fet is can now be switched on (uvp/ocp = v ss ) by the microcontroller by writing a ?1? to the uvpc bit of the control register. ? the status of the charge fet remains unaffected (on) ? the battery cells continue to receive charge via the charge fet and discharge fet (both on). table 22. over-discharge protection mode?event diagram description (continued) event event description X3100, x3101
19 fn8110.0 april 11, 2005 over-current protection in addition to monitoring the battery cell voltages, the X3100 and x3101 continually monitor the voltage vcs 21 (vcs 2 - vcs 1 ) across the curr ent sense resis- tor (r sense ). if vcs 21 > v oc for a time exceeding t oc , then the device enters over-current protection mode (figure 7). in this mode, the X3100 and x3101 automatically switch the discharge fet off (uvp/ocp = vcc) and hence prevent current from flowing through the terminals p+ and p-. figure 7. over-current protection the 5vdc voltage regulator output (v rgo ) is always active during an over-current protection mode. once the device enters over-current protection mode, the X3100 and x3101 begin a load monitor state. in the load monitor state, a small current (i lmon = 7.5a typ.) is passed out of pin ovp/lmon in order to deter- mine the load resistance. the load resistance is the impedance seen looking out of pin ovp/lmon, between terminal p+ an d pin vss (see figure 7.) if the load resistance > r ocr (i lmon = 0a) for a time exceeding t ocr , then the X3100 or x3101 is released from over-current protection mode. the discharge fet is then automatically swit ched on (uvp/ocp = vss) by the X3100 or x3101, unle ss the status of uvp/ocp has been changed in control register (by manipulating bit uvpc) during the over-c urrent protection mode. t oc /t ocr are varied using a capacitor (c oc ) con- nected between pin oct an d vss. a list of typical delay times is shown in table 23. note that the value c oc should be larger than 1nf. the delay t oc and t ocr that results from a particular capacitance c oc can be approximated by the follow- ing equations: t oc (ms) 10,000 x c oc (f) t ocr (ms) 10,000 x c oc (f) table 23. typical over-current delay times the value of v oc can be selected from the values shown in table 6, by setting bits voc1, voc0 in the configuration register using the wcfig command. note: if the charge fet is tu rned off, due to an over- charge condition or by dire ct command from the micro- controller, the cells are not in an undervoltage condition and the pack has a load, then excessive cur- rent may flow through q10 and diode d1. to eliminate this effect, the gate of q10 can be turned off by the microcontroller through an unused x3101 cell balance output, or directly from a microcontroller port instead of connecting to v rgo . fet control circuitry ovp/lmon q2 d1 i lmon X3100/x3101 p+ p- r ocr vcs1 vcs2 vss r sense v rgo q10 (load) symbol description c oc delay t oc over-current detection delay 0.001 f 10ms (typ) t ocr over-current release time 0.001 f 10ms (typ) X3100, x3101
20 fn8110.0 april 11, 2005 figure 8. over-current protection mode?event diagram p+ vcs 2 uvp/ocp t ocr v ss over-current protection mode t oc voc normal operation mode p+ = (rload+rsense) x ilmon v oc normal operation mode event 0 1 3 4 2 v ss v cc b+ table 24. over-current protection mode?event diagram description event event description [0,1) ? discharge fet is on (ocp = vss). ba ttery cells are permitted to discharge. ?vcs 21 (vcs 2 - vcs 1 ) is less than the over-current threshold voltage (v oc ). ? the device is in normal operation mode (i.e. not in a protection mode). [1] ? excessive current flows through the battery terminals p+, dropping the voltage. (see figure 8.). ? the positive battery terminal voltage (p+) falls, and vcs 21 exceeds v oc . ? the internal over-current detection delay timer begins counting down. ? the device is still in normal operation mode (1,2) the internal over-current detection delay timer continues counting for t oc seconds. [2] ? the internal over-current detection delay timer times out, and vcs 21 is still above v oc. ? the internal over-current sense circuitry s witches the discharge fet off (uvp/ocp = vcc). ? the device now begins a load monitor state by passing a small test current (i lmon = 7.5a) out of pin ovp/lmon. this senses if an over-current condition (i.e. if the load resistance < r ocr ) still exists across p+/p-. ? the device has now entered over-current protection mode. ? it is possible to change the status of uvpc and ovpc in the control regi ster, although the status of pins uvp/ocp and ovp/lmon will not change until the device has returned from over-current protection mode. (2,3) ? the X3100/x3101 now continuously monitors the l oad resistance to detect whether or not an over- current condition is still present across the battery terminals p+/p-. X3100, x3101
21 fn8110.0 april 11, 2005 monitor mode analog multiplexer selection the X3100 and x3101 can be used to externally monitor individual battery cell voltages, and battery current. each quantity can be monitored at the analog output pin (ao), and is selected using the analog select (as0 - as2) pins (table 25). also, see figure 9. current monitor function the voltages monitored at pins vcs 1 and vcs 2 can be used to calculate current flowing through the battery terminals, using an off-board microcontroller with an a/d. since the value of th e sense resistor (r sense ) is small (typically in the order of tens of m ? ), and since the resolution of various a/d converters may vary, the voltage across r sense ( vcs 1 and vcs 2 ) is amplified internally with a gain of between 10 and 160, and out- put to pin ao (figure 9). figure 9. X3100/x3101 monitor circuit [3] ? the device detects the load resistance has risen above r ocr . ? voltages p+ and vcs 21 return to their normal levels. ? the test current from pin ovp/lmon is stopped (i lmon = 0a) ? the device has now returned from the load monitor state ? the internal over-current release time timer begins counting down. ? device is still in over-current protection mode. (3,4) the internal over-current release timer continues counting for t ocr seconds. [4] ? the internal over-current release timer times out, and vcs 21 is still below v oc. ? the device returns from over-current protec tion mode, and is now in normal operation mode. ? the discharge fet is automatically switched on (uvp /ocp = vss)?unless the status of uvpc has been changed in the control register during the over-current protection mode. ? the status of the charge fet remains unaffected. ? discharge of the battery cells is once again possible. table 24. over-current protection mode?event diagram description (continued) event event description table 25. ao selection map as2 as1 as0 ao output lllv ss (1) llhvcell 1 - vcell 2 (vcell 12 ) lhlvcell 2 - vcell 3 (vcell 23 ) lhhvcell 3 - vcell 4 (vcell 34 ) hllvcell 4 - vss (vcell 4 ) hlhvcs 1 - vcs 2 (vcs 12 ) (2) hhlvcs2 - vcs 1 (vcs 21 ) (2) hhhv ss notes: (1) this is the normal state of the X3100 or x3101. while in this state over-charge and over-discharge protec- tion conditions are periodically monitored (see ?peri- odic protection monitoring? on page 13.) (2) vcs 1 , vcs 2 are read at ao with respect to a dc bias voltage of 2.5v (see section ?current monitor func- tion? on page 21). over-current protection vcs 1 vcs 2 + - csg1 csg0 config register a nalog mux as0 as1 as2 ao spi i/f s0 scl cs si r sense gain setting cross-bar switch X3100/x3101 op1 voltage level shifters cell 1 voltage cell 2 voltage cell 3 voltage cell 4 voltage 2.5v p- r2 r2 r1 r1 X3100, x3101
22 fn8110.0 april 11, 2005 the internal gain of the X3100 or x3101 current sense voltage amplifier can be selected by using the wcntr instruction to set bits csg1 and csg0 in the control register (table 14). the csg1 and csg0 bits select one of four input resistors to op amp op1. the feed- back resistors remain constant. this ratio of input to feedback resistors determines the gain. putting exter- nal resistors in series with the inputs reduces the gain of the amplifier. vcs 1 and vcs 2 are read at ao with respect to a dc bias voltage of 2.5v. therefore, the voltage range of vcs 12 and vcs 21 changes depending upon the direc- tion of current flow (i.e. battery cells are in charge or discharge?table 21). table 26. ao voltage range for vcs 12 and vcs 21 by calculating the difference of vcs 12 and vcs 21 the offset voltage of the internal op-amp circuitry is can- celled. this allows for the accurate calculation of cur- rent flow into and out of the battery cells. pack current is calculated using the following formula: voltage regulator the X3100 and x3101 are able to supply peripheral devices with a regulated 5vdc0.5% output at pin rgo. the voltage regulator should be configured externally as shown in figure 10. the non-inverting input of op1 is fed with a high preci- sion 5vdc supply. the volt age at the output of the voltage regulator (v rgo ) is compared to this 5v refer- ence via the inverting input of op1. the output of op1 in turn drives the regulator pnp transistor (q1). the negative feedback at the regulator output maintains the voltage at 5vdc0.5% (including ripple) despite changes in load, and differences in regulator transistors. when power is applied to pin vcc of the X3100 or x3101, v rgo is regulated to 5vdc10% for a nominal time of t oc +2ms. during this time period, v rgo is ?tuned? to attain a final val ue of 5vdc0.5% (figure 2). the maximum current that can flow from the voltage regulator (i lmt ) is controlled by the current limiting resistor (r lmt ) connected between rgp and vcc. when the voltage across vcc and rgp reaches a nominal 2.5v (i.e. the thresh old voltage for the fet), q2 switches on, shorting vcc to the base of q1. since the base voltage of q1 is now higher than the emitter voltage, q1 switches off, and hence the supply current goes to zero. typical values for r lmt and i lmt are shown in table 27. in order to protect the voltage regulator circuitry from damage in case of a short-circuit, r lmt 10 ? should always be used. table 27. typical values for r lmt and i lmt when choosing the value of r lmt , the drive limitations of the pnp transistor used should also be taken into consideration. the transistor should have a gain of at least 100 to support an output current of 250ma. figure 10. voltage regulator operation 4kbit eeprom memory the X3100 and x3101 contain a cmos 4k-bit serial eeprom, internally organized as 512 x 8 bits. this memory is accessible via the spi port, and features the idlock function. ao cell state ao voltage range vcs 12 charge 2.5v ao 5.0v vcs 12 discharge 0v ao 2.5v vcs 21 charge 0v ao 2.5v vcs 21 discharge 2.5v ao 5.0v pack current vcs 12 vcs 21 ? () 2 () gain setting () (current sense resistor) --------------------------------------------------------------------------------------------------------- - = r lmt voltage regulator current limit (i lmt ) 10 ? 250ma 50% (typical) 25 ? 100ma 50% (typical) 50 ? 50ma 50% (typical) vcc rgc rgp rgo voltage reference _ + to internal voltage regulating circuitry regulated 5vdc output r lmt q1 un-regulated input voltage i lmt precision X3100/x3101 op1 5vdc q2 tuning v rgo 0.1 f X3100, x3101
23 fn8110.0 april 11, 2005 the 4kbit eeprom array c an be accessed by the spi port at any time, even duri ng a protection mode, except during sleep mode. after power is applied to vcc of the X3100 or x3101, eeread and eewrite instructions can be executed only after times t pur (power-up to read time) and t puw (power-up to write time) respec- tively. idlock is a programmable locking mechanism which allows the user to lock data in different portions of the eeprom memory space, ranging from as little as one page to as much as 1/2 of the total array. this is useful for storing information such as battery pack serial number, manufacturing codes, battery cell chemistry data, or cell characteristics. eeprom write enable latch the X3100 and x3101 contain an eeprom ?write enable? latch. this latch mu st be set before a write to eeprom operation is initiat ed. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 11). this latch is automatically reset upon a power-up condition and after the completion of a byte or page write cycle. idlock memory intersil?s idlock memory pr ovides a flexible mecha- nism to store and lock battery cell/pack information. there are seven distinct idlock memory areas within the array which vary in size from one page to as much as half of the entire array. prior to any attempt to perform an idlock operation, the wren instruction must first be issued. this instruction sets the ?write enable? latch and allows the part to respond to an idlock sequence. the eeprom memory may then be idlocked by writing the set idl instruction (table 30 and figure 19), followed by the idlock protection byte. table 28. idlock partition byte definition the idlock protection byte contains the idlock bits idl2-idl0, which defines the particular partition to be locked (table 28). the rest of the bits [7:3] are unused and must be written as zeroes. bringing cs high after the two byte idlock instruction initiates a nonvola- tile write to the status register. writing more than one byte to the status register will overwrite the previously written idlock byte. once an idlock instruction has been completed, that idlock setup is held in a nonvolatile idlock register (table 29) until the next idlock instruction is issued. the sections of the memory array that are idlocked can be read but not written until idlock is removed or changed. table 29. idlock register X3100/x3101 spi ser ial communication the X3100 and x3101 are designed to interface directly with the synchronous serial peripheral inter- face (spi) of many popula r microcontroller families. this interface uses four signals, cs , sck, si and so. the signal cs when low, enables communications with the device. the si pin carries the input signal and so provides the output signal. sck clocks data in or out. the X3100 and x3101 operate in spi mode 0 which requires sck to be normally low when not transferring data. it also specifies that the rising edge of sck clocks data into th e device, while the falling edge of sck clocks data out. this spi port is used to set the various internal regis- ters, write to the eeprom array, and select various device functions. the X3100 and x3101 contain an 8-bit instruction register. it is accessed by clocking data into the si input. cs must be low during the entire operation. table 30 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb first. data input is sampled on the first rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock, and then start it again to resume opera- tions where left off. idlock protection bytes eeprom memory address idlocked 0000 0000 none 0000 0001 000h - 07fh 0000 0010 080h - 0ffh 0000 0011 100h - 17fh 0000 0100 180h - 1ffh 0000 0101 000h - 0ffh 0000 0110 000h - 00fh 0000 0111 1f0h - 1ffh 76543 2 1 0 0 0 0 0 0 idl2 idl1 idl0 note: bits [7:3] specified to be ?0?s? X3100, x3101
24 fn8110.0 april 11, 2005 write enable/write disable (wren/wrdi) any write to a nonvolatile array or register, requires the wren command be sent prior to the write com- mand. this command sets an internal latch allowing the write operation to pr oceed. the wrdi command resets the internal latch if the system decides to abort a write operation. see figure 11. figure 11. eeprom write enable latch (wren/wrdi) operation sequence table 30. X3100/x3101 instruction set instruction name instruction format* description wren 0000 0110 set the write enable latch (write enable operation)?figure 11 wrdi 0000 0100 reset the write enable latch (write disable operation)?figure 11 eewrite 0000 0010 write command followed by addre ss/data (4kbit eeprom)?figure 12, figure 13 eeread stat 0000 0101 reads idlock settings & stat us of eeprom eewrite instruction?figure 14 eeread 0000 0011 read operation followed by address (for 4kbit eeprom)?figure 15 wcfig 0000 1001 write to configuration register followed by two bytes of data?figure 4, figure 16. data stored in sram only and will power-up to previous settings?figure 3 wcntr 0000 1010 write to control register, followed by two bytes of data?figure 17 rdstat 0000 1011 read contents of status register?figure 18 set idl 0000 0001 set eeprom id lock partiti on followed by partition byte?figure 19 *instructions have the msb in leftmost position and are transferred msb first. 01234567 cs si sck high imped ance so instruction (1 byte) wren wrdi X3100, x3101
25 fn8110.0 april 11, 2005 eeprom write sequence (eewrite) prior to any attempt to write data into the eeprom of the X3100 or x3101, the ?write enable? latch must first be set by issuing the wren instruction (see table 30 and figure 11). cs is first taken low. then the wren instruction is clocked into the X3100 or x3101. after all eight bits of the instruction are transmitted, cs must then be taken high. if the us er continues the write operation without taking cs high after issuing the wren instruction, the wr ite operation will be ignored. to write data to the eeprom memory array, the user issues the eewrite instruction, followed by the 16 bit address and the data to be written. only the last 9 bits of the address are used and bits [15:9] are specified to be zeroes. this is minimally a thirty-two clock opera- tion. cs must go low and remain low for the dura- tion of the operation. the host may continue to write up to 16 bytes of data to the X3100 or x3101. the only restriction is the 16 bytes must reside on the same page. if the address counter reaches the end of the page and the clock contin ues, the counter will ?roll over? to the first address of the page and overwrite any data that may have been previously written. for a byte or page write operation to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed. refer to figure 12 and figure 13 for detailed illustration of th e write sequences and time frames in which cs going high are valid. eeprom read status op eration (eeread stat) if there is not a nonvolatile write in progress, the eeread stat instruction returns the idlock byte from the idlock register which contains the idlock bits idl2-idl0 (table 29). the idlock bits define the idlock condition (table 28). the other bits are reserved and will retu rn ?0? when read. if a nonvolatile write to the eeprom (i.e. eewrite instruction) is in progres s, the eeread stat returns a high on so. when the nonvolatile write cycle in the eeprom is completed, the status register data is read out. clocking sck is valid during a nonvolatile write in progress, but is not necessary. if the sck line is clocked, the pointer to the status register is also clocked, even though the so pin shows the status of the nonvolatile write opera tion (see figure 14). figure 12. eeprom by te write (eewrite) operation sequence 0123456789 cs sck si so high impedance eewrite instruction (1 byte) byte address (2 byte) data byte 1514 3210 20 21 22 23 24 25 26 27 28 29 30 31 76543210 X3100, x3101
26 fn8110.0 april 11, 2005 figure 13. eeprom page write (eewrite) operation sequence figure 14. eeprom read status (eeread stat) operation sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si eewrite instruction byte address (2 byte) 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 6543210 data byte 16 data byte 1 146 145 147 149 148 150 151 01234567 cs sck si so nonvolatile eewrite in progress eeread stat instruction i so high during nonvolatile eewrite cycle so=status reg bit when no nonvolatile eewrite cycle ... ... ... d l 2 i d l 1 i d l 0 X3100, x3101
27 fn8110.0 april 11, 2005 eeprom read sequence (eeread) when reading from the X3100 or x3101 eeprom memory, cs is first pulled low to select the device. the 8-bit eeread instruction is transmitted to the X3100 or x3101, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be zeroes). after the eeread opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (01ffh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the eeprom read (eeread) operation sequence illustrated in figure 15. figure 15. eeprom (eeread) read operation sequence 0123456789 cs sck si so high impedance eeread instruction (1 byte) byte address (2 byte) data out 15 14 3210 20 21 22 23 24 25 26 27 28 29 30 76543210 31 X3100, x3101
28 fn8110.0 april 11, 2005 write configuration register (wcfig) the write configuration register (wcfig) instruc- tion updates the static part of the configuration reg- ister. these new values take effect immediately, for example writing a new over-discharge voltage limit. however, to make these changes permanent, so they remain if the cell voltages are removed, an eewrite operation to the eeprom a rray is required following the wcfig command. this command is shown in figure 16. write control register (wcntrl) the write control register (wcntrl) instruction updates the contents of the volatile control register. this command sets the status of the fet control pins, the cell balancing outputs, the current sense gain and external entry to the sleep mode. since this instruction controls a volatile register, no other commands are required and there is no delay time needed after the instruction, before subsequent commands. the operation of the wcntrl command is shown in figure 17. figure 16. write configuration re gister (wcfig) operation sequence figure 17. write control register (wcntr) operation sequence 0123456789 cs sck si so high impedance wcfig instruction (1 byte) configuration 15 14 3210 20 21 22 23 register data (2 byte) 0123456789 cs sck si so high impedance wcntr instruction (1 byte) control 15 14 5432 18 19 20 21 register data (2 byte) 22 23 1 0 old control bits new control bits control bits X3100, x3101
29 fn8110.0 april 11, 2005 read status register (rdstat) the read status register (rdstat) command returns the status of the X3100 or x3101. the status register contains three bits that indicate whether the voltage regulator is stabilized, and if there are any pro- tection failure conditions . the operation of the rdstat instruction is shown in figure 18. set id lock (set idl) the contents of the eeprom memory array in the X3100 or x3101 can be locked in one of eight configu- rations using the set id lock command. when a sec- tion of the eeprom arra y is locked, the contents cannot be changed, even when a valid write operation attempts a write to that area. the set idl command operation is shown in figure 19. figure 18. read status register (rdstat) operation sequence figure 19. eeprom idlock (set idl) operation sequence 012345678 cs sck si so high impedance instruction (1 byte) 9 101112131415 210 rdstat status register output 0123456789 cs sck si so high impedance set idl 10 11 12 13 14 15 idlock byte instruction i d l 2 i d l 1 i d l 0 X3100, x3101
30 fn8110.0 april 11, 2005 absolute maximum ratings stresses above those listed under ?absolute maximum ratings? may caus e permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other condi tions above those indicated in the operational sections of this specification) is not im plied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. recommended operating conditions d.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) symbol parameter min. max. unit storage temperature -55 125 c operating temperature -40 85 c dc output current 5 ma lead temperature (soldering 10 seconds) 300 c vcc power supply voltage v ss -0.5 v ss +27.0 v vcell cell voltage -0.5 6.75 v v term1 terminal voltage (pins: sck, si, so, cs, as0, as1, as2, vcs1, vcs2, ovt, uvt, oct, ao) v ss -0.5 v rgo + 0.5 v v term 2 terminal voltage (vcell1) v ss -0.5 v cc + 1.0 v v term 3 terminal voltage (all other pins) v ss -0.5 v cc + 0.5 v temperature min. max. supply voltage limits commercial -20c +70c X3100/x3101 6v to 24v symbol parameter limits units test conditions min. max. i li input leakage current (sck, si, cs , aso, as1, as2) 10 a i lo output leakage current (so) 10 a v il (1) input low voltage (sck, si, cs , as0, as1, as2) - 0.3 v rgo x 0.3 v v ih (1) input high voltage (sck, si, cs , as0, as1, as2) v rgo x 0.7 v rgo + 0.3 v vol1 output low voltage (so) 0.4 v i ol = 1.0ma voh1 output high voltage (so) v rgo - 0.8 v i oh = -0.4ma vol2 output low voltage (uvp/ocp, ovp/lmon, cb1-cb4) 0.4 v i ol = 100ua voh2 output high voltage (uvp/ocp, ovp/lmon, cb1-cb4) v cc -0.4 v i oh = -20ua vol3 output low voltage (rgc) 0.4 v i ol = 2ma, rgp = v cc , rgo = 5v voh3 output high voltage (rgc) v cc -4.0 v i oh = -20a, rgp = v cc - 4v, rgo = 5v note: (1) v il min. and v ih max. are for reference only and are not 100% tested. X3100, x3101
31 fn8110.0 april 11, 2005 operating characteristics X3100 (over the recommended operating cond itions unless otherwise specified) description sym condition min typ (2) max unit 5v regulated voltage v rgo on power-up or at wake-up 4.5 5.5 v after self-tuning (@10ma v rgo current; 25 o c) 4.98 4.99 5.00 after self-tuning (@10ma v rgo current; 0 - 50 o c) (5) 4.95 5.02 after self-tuning (@50ma v rgo current) (5) 4.90 5.00 v 5vdc voltage regulator current limit i lmt (3) r lmt = 10 ? 250 ma v cc supply current (1) icc1 normal operation 85 250 a v cc supply current (2) icc2 during nonvolatile eeprom write 1.3 2.5 ma v cc supply current (3) icc3 during eeprom read sck=3.3mhz 0.9 1.2 ma v cc supply current (4) icc4 sleep mode 1 a v cc supply current (5) icc5 monitor mode an2, an1, an0 not equal to 0. 365 600 a cell over-charge protection mode voltage threshold (default in boldface) v ov (4) v ov = 4.20v (vov1, vov0 = 0,0) 0 o c to 50 o c 4.10 4.15 4.275 4.25 v v ov = 4.25v (vov1, vov0 = 0,1) 0 o c to 50 o c 4.15 4.20 4.325 4.30 v v ov = 4.30v (vov1, vov0 = 1,0) 0 o c to 50 o c 4.2 4.25 4.375 4.35 v v ov = 4.35v (vov1, vov0 = 1,1) 0 o c to 50 o c 4.25 4.425 v 4.30 4.40 cell over-charge protection mode release voltage threshold v ovr v ov - 0.20 v cell over-charge detection time t ov c ov = 0.1uf 1 s cell over-discharge protection mode (sleep) threshold. (default in boldface) v uv (4) v uv = 1.95v (vuv1, vuv0 = 0,0) 1.85 2.05 v v uv = 2.05v (vuv1, vuv0 = 0,1) 1.95 2.15 v v uv = 2.15v (vuv1, vuv0 = 1,0) 2.05 2.25 v v uv = 2.25v (vuv1, vuv0 = 1,1) 2.15 2.35 v cell over-discharge protection mode release threshold v uvr v uv + 0.7 v cell over-discharge detection time t uv c uv = 0.1f c uv = 200pf 1 2 s ms cell over-discharge release time t uvr c uv = 0.1f c uv = 200pf 7 100 ms s X3100, x3101
32 fn8110.0 april 11, 2005 notes: (2) typical at 25c. (3) see figure 10 on page 22. (4) the default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register . (5) for reference only, this parameter is not 100% tested. wake-up test circuit (X3100) sleep test circuit (X3100) over-current mode detection voltage (default in boldface) v oc (4) v oc = 0.075v (voc1, voc0 = 0,0) 0 o c to 50 o c 0.050 0.060 0.100 0.090 v v oc = 0.100v (voc1, voc0 = 0,1) 0 o c to 50 o c 0.075 0.085 0.125 0.115 v v oc = 0.125v (voc1, voc0 = 1,0) 0 o c to 50 o c 0.100 0.110 0.150 0.140 v v oc = 0.150v (voc1, voc0 = 1,1) 0 o c to 50 o c 0.125 0.135 0.175 0.165 v over-current mode detection time t oc c oc = 0.001 f c oc = 200pf 10 2 ms over-current mode release time t ocr c oc = 0.001 f c oc = 200pf 10 2 ms load resistance over-current mode release condition r ocr releases when ovp/lmon pin > 2.5v 250 k ? cell charge threshold voltage v ce (4) v ce = 0.5v (vce1, vce0 = 0,0) 0.4 0.5 0.6 v v ce = 0.8v (vce1, vce0 = 0,1) 0.7 0.8 0.9 v v ce = 1.1v (vce1, vce0 = 1,0) 1 1.1 1.2 v v ce = 1.4v (vce1, vce0 = 1,1) 1.3 1.4 1.5 v X3100 wake-up voltage (for vcc above this voltage, the device wakes up) v slr see wake-up test circuit 12.5 15.5 v X3100 sleep voltage (for vcc above this voltage, the device cannot go to sleep) v slp see sleep test circuit 11.5 14.5 v description sym condition min typ (2) max unit vcc vcc vcell1 vcell2 vcell3 vcell4 vss rgp rgc rgo increase vcc until v rgo turns on v rgo vcc vcc vcell1 vcell2 vcell3 vcell4 vss rgp rgc rgo 1v 1v 1v 1v decrease vcc until v rgo turns off v rgo X3100, x3101
33 fn8110.0 april 11, 2005 operating characteristics x3101 (over the recommended operating cond itions unless otherwise specified) description sym condition min typ (2) max unit 5v regulated voltage v rgo on power-up or at wake-up 4.5 5.5 v after self-tuning (@10ma v rgo current; 25 o c) 4.98 4.99 5.00 after self-tuning (@10ma v rgo current; 0 - 50 o c) (5) 4.95 5.02 after self-tuning (@50ma v rgo current) (5) 4.90 5.00 v 5vdc voltage regulator current limit i lmt (3) r lmt = 10 ? 250 ma v cc supply current (1) icc1 normal operation 85 250 a v cc supply current (2) icc2 during nonvolatile eeprom write 1.3 2.5 ma v cc supply current (3) icc3 during eeprom read sck = 3.3mhz 0.9 1.2 ma v cc supply current (4) icc4 sleep mode 1 a v cc supply current (5) icc5 monitor mode an2, an1, an0 not equal to 0. 365 600 a cell over-charge protection mode voltage threshold (default in boldface) v ov (4) v ov = 4.20v (vov1, vov0 = 0,0) 0 o c to 50 o c 4.10 4.15 4.275 4.25 v v ov = 4.25v (vov1, vov0 = 0,1) 0 o c to 50 o c 4.15 4.20 4.325 4.30 v v ov = 4.30v (vov1, vov0 = 1,0) 0 o c to 50 o c 4.2 4.25 4.375 4.35 v v ov = 4.35v (vov1, vov0 = 1,1) 0 o c to 50 o c 4.25 4.425 v 4.30 4.40 cell over-charge protection mode release voltage threshold v ovr v ov - 0.20 v cell over-charge detection time t ov c ov = 0.1uf 1 s cell over-discharge protection mode (sleep) threshold. (default in boldface) v uv (4) v uv = 2.25v (vuv1, vuv0 = 0,0) 2.15 2.35 v v uv = 2.35v (vuv1, vuv0 = 0,1) 2.25 2.45 v v uv = 2.45v (vuv1, vuv0 = 1,0) 2.35 2.55 v v uv = 2.55v (vuv1, vuv0 = 1,1) 2.45 2.65 v cell over-discharge protection mode release threshold v uvr v uv + 0.7 v cell over-discharge detection time t uv c uv = 0.1f c uv = 200pf 1 2 s ms cell over-discharge release time t uvr c uv = 0.1f c uv = 200pf 7 100 ms s X3100, x3101
34 fn8110.0 april 11, 2005 notes: (2) typical at 25c. (3) see figure 10 on page 22. (4) the default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register . (5) for reference only, this parameter is not 100% tested. wake-up test circuit (x3101) sleep test circuit (x3101) over-current mode detection voltage (default in boldface) v oc (4) v oc = 0.075v (voc1, voc0 = 0,0) 0 o c to 50 o c 0.050 0.060 0.100 0.090 v v oc = 0.100v (voc1, voc0 = 0,1) 0 o c to 50 o c 0.075 0.085 0.125 0.115 v v oc = 0.125v (voc1, voc0 = 1,0) 0 o c to 50 o c 0.100 0.110 0.150 0.140 v v oc = 0.150v (voc1, voc0 = 1,1) 0 o c to 50 o c 0.125 0.135 0.175 0.165 v over-current mode detection time t oc c oc = 0.001 f c oc = 200pf 10 2 ms over-current mode release time t ocr c oc = 0.001 f c oc = 200pf 10 2 ms load resistance over-current mode release condition r ocr releases when ovp/lmon pin > 2.5v 250 k ? cell charge threshold voltage v ce v ce = 0.5v (vce1, vce0 = 0,0) 0.4 0.5 0.6 v v ce = 0.8v (vce1, vce0 = 0,1) 0.7 0.8 0.9 v v ce = 1.1v (vce1, vce0 = 1,0) 1 1.1 1.2 v v ce = 1.4v (vce1, vce0 = 1,1) 1.3 1.4 1.5 v x3101 wake-up voltage (for vcc above this voltage, the device wakes up) v slr see wake-up test circuit 10.5 12.5 v x3101 sleep voltage (for vcc above this voltage, the device cannot go to sleep) v slp see sleep test circuit 9.5 11.5 v description sym condition min typ (2) max unit increase vcc until v rgo turns on vcc v rgo vcc vcell1 vcell2 vcell3 vcell4 vss rgp rgc rgo vcc vcc vcell1 vcell2 vcell3 vcell4 vss rgp rgc rgo 1v 1v 1v decrease vcc until v rgo turns off v rgo X3100, x3101
35 fn8110.0 april 11, 2005 power-up timing notes: (6) t pur , t puw1 and t puw2 are the delays required from the time v cc is stable until a read or write can be initiated. these parameters are not 100% tested. (7) whichever is longer. capacitance t a = +25c, f = 1 mhz, v rgo = 5v equivalent a.c. load circuit a.c. test conditions symbol parameter min. max. t pur (6) power-up to spi read operati on (rdstat, eeread stat) t oc + 2ms t puw1 (6) power-up to spi write operation (wren, wrdi, eewrite, wcfig, set idl, wcntr) t oc + 2ms t puw2 (6) power-up to spi write operation (wcntr - bits 10 and 11) t ov + 200ms or t uv + 200ms (7) symbol parameter max. units conditions c out (8) output capacitance (so) 8 pf v out = 0v c in (8) input capacitance (sck, si, cs )6pfv in = 0v notes: (8) this parameter is not 100% tested. so 5v 2061 ? 3025 ? 30pf input pulse levels 0.5 - 4.5v input rise and fall times 10ns input and output timing level 2.5v X3100, x3101
36 fn8110.0 april 11, 2005 a.c. characteristics (over the recommended operating condit ions, unless otherwise specified.) serial input timing notes: (9) this parameter is not 100% tested (10)t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. serial input timing symbol parameter voltage min. max. units f sck clock frequency 0 3.3 mhz t cyc cycle time 300 ns t lead cs lead time 150 ns t lag cs lag time 150 ns t wh clock high time 130 ns t wl clock low time 130 ns t su data setup time 20 ns t h data hold time 20 ns t ri (9) data in rise time 2 s t fi (9) data in fall time 2 s t cs cs deselect time 100 ns t wc (10) write cycle time 5 ms sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi X3100, x3101
37 fn8110.0 april 11, 2005 serial output timing notes: (11)this parameter is not 100% tested. serial output timing symbol table symbol parameter vol tage min. max. units f sck clock frequency 0 3.3 mhz t dis output disable time 150 ns t v output valid from clock low 130 ns t ho output hold time 0 ns t ro (11) output rise time 50 ns t fo (11) output fall time 50 ns sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance X3100, x3101
38 fn8110.0 april 11, 2005 analog output response time analog output response time change in voltage source change in current sense gain amplification and control bits symbol parameter m in. typ. max. units t vsc ao output stabilization time (voltage source change) 1.0 ms t csgo ao output stabilization time (current sense gain change) 1.0 ms t co control outputs response time (uvp/ocp, ovp/mon, cb4, cb3, cb2, cb1, rgc) 1.0 s as2:as0 ao t vsc t vsc old gain new gain ovpc csg1 csg0 slp 00 x c s sck di control reg ao gain change uvp/ocp control on off outputs ovp/lmon cb4:cb1 rgc bit10 bit9 bit8 bit7 bit6 bit5 current sense t csgo t co X3100, x3101
39 fn8110.0 april 11, 2005 typical operating characteristics X3100/x3101 over charge trip voltage (typical) 4.15 4.20 4.25 4.30 4.35 4.40 -25 25 75 temperature (deg c) voltage (v) 4.2v setting 4.25v setting 4.3v setting 4.35v setting X3100 over discharge trip voltage (typical) 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 -25 25 75 temperature (deg c) voltage (v) 1.95v setting 2.05v setting 2.15v setting 2.25v setting voltage regulator output (typical) vcc = 10.8v to 16v r lim =15ohm(i lim =200ma) 4.880 4.900 4.920 4.940 4.960 4.980 5.000 5.020 11050100 load (ma) regulator voltage (v) -25 degc 25 degc 75 degc voltage regulator output (typical) vcc = 10.8v to 16v r lim =15ohm(i lim =200ma) 4.880 4.900 4.920 4.940 4.960 4.980 5.000 5.020 -25 25 75 temperature regulated voltage 1ma load 10ma load 50ma load 100maload x3101 over discharge trip voltage (typical) 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -25 25 75 temperature (deg c) voltage (v) 2.25v setting 2.35v setting 2.45v setting 2.55v setting no r m al op e r at in g cu r r e n t 50 75 100 125 150 -20 25 80 temperature current (ua) monitor mode current 300 350 400 450 -20 25 80 temperature current (ua) for typical performance of current and voltage monitoring circuits, please refer to application note an142 and an143 X3100, x3101
40 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8110.0 april 11, 2005 note: all dimensions in inches (in parentheses in millimeters) .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .377 (9.60) .385 (9.80) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) 0 - 8 .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 28-lead plastic, tssop, package code v28 X3100, x3101

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